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TJA1021
LIN 2.1/SAE J2602 transceiver
Rev. 6 -- 30 December 2010 Product data sheet
1. General description
The TJA1021 is the interface between the Local Interconnect Network (LIN) master/slave protocol controller and the physical bus in a LIN. It is primarily intended for in-vehicle sub-networks using baud rates from 1 kBd up to 20 kBd and is LIN 2.1/SAE J2602 compliant. The TJA1021 is pin-to-pin compatible with the TJA1020 with an improved ElectroStatic Discharge (ESD) specification. The transmit data stream of the protocol controller at the transmit data input (TXD) is converted by the TJA1021 into a bus signal with optimized slew rate and wave shaping to minimize ElectroMagnetic Emission (EME). The LIN bus output pin is pulled HIGH via an internal termination resistor. For a master application, an external resistor in series with a diode should be connected between pin INH or pin VBAT and pin LIN. The receiver detects the data stream at the LIN bus input pin and transfers it via pin RXD to the microcontroller. In Sleep mode, the power consumption of the TJA1021 is very low. In failure modes, the power consumption is reduced to a minimum.
2. Features and benefits
2.1 General
LIN 2.1/SAE J2602 compliant Baud rate up to 20 kBd Very low ElectroMagnetic Emission (EME) High ElectroMagnetic Immunity (EMI) Passive behavior in unpowered state Input levels compatible with 3.3 V and 5 V devices Integrated termination resistor for LIN slave applications Wake-up source recognition (local or remote) Supports K-line like functions Pin-to-pin compatible with TJA1020
2.2 Low power management
Very low current consumption in Sleep mode with local and remote wake-up
2.3 Protection mechanisms
High ESD robustness: 6 kV according to IEC 61000-4-2 for pins LIN, VBAT and WAKE_N Transmit data (TXD) dominant time-out function
NXP Semiconductors
TJA1021
LIN 2.1/SAE J2602 transceiver
Bus terminal and battery pin protected against transients in the automotive environment (ISO 7637) Bus terminal short-circuit proof to battery and ground Thermally protected
3. Quick reference data
Table 1. VBAT IBAT Quick reference data Conditions with respect to GND Sleep mode; VLIN = VBAT; VWAKE_N = VBAT VTXD = 0 V; VSLP_N = 0 V Standby mode; bus recessive VINH = VBAT; VLIN = VBAT; VWAKE_N = VBAT VTXD = 0 V; VSLP_N = 0 V Standby mode; bus dominant VBAT = 12 V; VINH = 12 V; VLIN = 0 V VWAKE_N = 12 V; VTXD = 0 V; VSLP_N = 0 V Normal mode; bus recessive VINH = VBAT; VLIN = VBAT; VWAKE_N = VBAT VTXD = 5 V; VSLP_N = 5 V Normal mode; bus dominant VBAT = 12 V; VINH = 12 V; VWAKE_N = 12 V VTXD = 0 V; VSLP_N = 5 V VLIN Tvj voltage on pin LIN virtual junction temperature with respect to GND, VBAT and VWAKE_N Min 0.3 2 150 Typ 7 450 Max +40 10 1000 Unit V A A battery supply voltage battery supply current Symbol Parameter
300
800
1200
A
300
800
1600
A
1
2
4
mA
40 40
-
+40 +150
V C
4. Ordering information
Table 2. Ordering information Package Name TJA1021T/10 TJA1021T/20 TJA1021TK/10 TJA1021TK/20
[1]
Type number[1]
Description plastic small outline package; 8 leads; body width 3.9 mm plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 3 0.85 mm
Version SOT96-1 SOT782-1
SO8 HVSON8
TJA1021T/10 and TJA1021TK/10: for the low slope version that supports baud rates up to 10.4 kBd (SAE J2602); TJA1021T/20 and TJA1021TK/20: for the normal slope version that supports baud rates up to 20 kBd.
TJA1021
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Product data sheet
Rev. 6 -- 30 December 2010
2 of 25
NXP Semiconductors
TJA1021
LIN 2.1/SAE J2602 transceiver
5. Block diagram
VBAT
7 WAKE-UP TIMER CONTROL 8 INH
WAKE_N
3
SLP_N
2
SLEEP/ NORMAL TIMER
TEMPERATURE PROTECTION 6 LIN
TXD
4
TXD TIME-OUT TIMER
TJA1021
1 RXD/ INT BUS TIMER FILTER 5 GND
RXD
001aae066
Fig 1.
Block diagram
TJA1021
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Product data sheet
Rev. 6 -- 30 December 2010
3 of 25
NXP Semiconductors
TJA1021
LIN 2.1/SAE J2602 transceiver
6. Pinning information
6.1 Pinning
terminal 1 index area RXD SLP_N RXD SLP_N WAKE_N TXD 1 2 8 7 INH WAKE_N 3 4 VBAT LIN GND TXD 5 GND 1 2 8 7 INH VBAT LIN
TJA1021TK
6
TJA1021T
3 4
015aaa231
6 5
015aaa232
Transparent top view
a. TJA1021T/10; TJA1021T/20: SO8 Fig 2. Pin configuration diagrams
b. TJA1021TK/10; TJA1021TK/20: HVSON8
6.2 Pin description
Table 3. Symbol RXD SLP_N WAKE_N TXD GND LIN VBAT INH
[1]
Pin description Pin 1 2 3 4 5[1] 6 7 8 Description receive data output (open-drain); active LOW after a wake-up event sleep control input (active LOW); controls inhibit output; resets wake-up source flag on TXD and wake-up request on RXD local wake-up input (active LOW); negative edge triggered transmit data input; active LOW output after a local wake-up event ground LIN bus line input/output battery supply voltage battery related inhibit output for controlling an external voltage regulator; active HIGH after a wake-up event
HVSON8 package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to board ground. For enhanced thermal and electrical performance, it is recommended that the exposed center pad also be soldered to board ground.
TJA1021
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 -- 30 December 2010
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NXP Semiconductors
TJA1021
LIN 2.1/SAE J2602 transceiver
7. Functional description
The TJA1021 is the interface between the LIN master/slave protocol controller and the physical bus in a Local Interconnect Network (LIN). The TJA1021 is LIN 2.1/SAE J2602 compliant and provides optimum ElectroMagnetic Compatibility (EMC) performance due to wave shaping of the LIN output. The TJA1021T/20 and TJA1021TK/20 are optimized for the maximum specified LIN transmission speed of 20 kBd; theTJA1021T/10 and TJA1021TK/10 are optimized for the LIN transmission speed of 10.4 kBd as specified by the SAE J2602.
7.1 Operating modes
The TJA1021 supports modes for normal operation (Normal mode), power-up (Power-on mode) and very-low-power operation (Sleep mode). An intermediate wake-up mode between Sleep and Normal modes is also supported (Standby mode). Figure 3 shows the state diagram.
Power-on
INH: high TERM. = 30 k RXD: floating TXD: weak pull-down Transmitter: off
t(SLP_N = 1) > tgotonorm
Normal
INH: high TERM. = 30 k RXD: receive data output TXD: transmit data input Transmitter: on
switching on VBAT
t(SLP_N = 1) > tgotonorm
t(SLP_N = 1) > tgotonorm t(SLP_N = 0) > tgotosleep
Sleep
INH: floating TERM. = high ohmic RXD: floating TXD: weak pull-down Transmitter: off t(WAKE_N = 0; after 10) > tWAKE_N or t(LIN = 01; after LIN = 0) > tBUS
Standby
INH: high TERM. = 30 k RXD: low TXD: wake source output Transmitter: off
001aae073
TERM.: slave termination resistor, connected between pins LIN and VBAT.
Fig 3.
State diagram
TJA1021
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Product data sheet
Rev. 6 -- 30 December 2010
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NXP Semiconductors
TJA1021
LIN 2.1/SAE J2602 transceiver
Table 4. Mode
Operating modes SLP_N 0 0 TXD (output) weak pull-down weak pull-down if remote wake-up; strong pull-down if local wake-up[2] RXD floating LOW[3] INH floating HIGH Transmitter off off Remarks no wake-up request detected wake-up request detected; in this mode the microcontroller can read the wake-up source: remote or local wake-up
[2][3][4]
Sleep mode Standby[1] mode
Normal mode
1
HIGH: recessive state HIGH: recessive state HIGH LOW: dominant state LOW: dominant state weak pull-down floating HIGH
Normal mode off
Power-on mode 0
[1] [2] [3] [4] [5]
[5]
Standby mode is entered automatically upon any local or remote wake-up event during Sleep mode. Pin INH and the 30 k termination resistor at pin LIN are switched on. The internal wake-up source flag (set if a local wake-up did occur and fed to pin TXD) will be reset after a positive edge on pin SLP_N. The wake-up interrupt (on pin RXD) is released after a positive edge on pin SLP_N. Normal mode is entered after a positive edge on SLP_N. As long as TXD is LOW, the transmitter is off. In the event of a short-circuit to ground on pin TXD, the transmitter will be disabled. Power-on mode is entered after switching on VBAT.
7.2 Sleep mode
This mode is the most power-saving mode of the TJA1021. Despite its extreme low current consumption, the TJA1021 can still be woken up remotely via pin LIN, or woken up locally via pin WAKE_N, or activated directly via pin SLP_N. Filters at the inputs of the receiver (LIN), of pin WAKE_N and of pin SLP_N prevent unwanted wake-up events due to automotive transients or EMI. All wake-up events must be maintained for a certain time period (twake(dom)LIN, twake(dom)WAKE_N and tgotonorm). Sleep mode is initiated by a falling edge on pin SLP_N in Normal mode. To enter Sleep mode successfully (INH becomes floating), the sleep command (pin SLP_N = LOW) must be maintained for at least tgotosleep. In Sleep mode the internal slave termination between pins LIN and VBAT is disabled to minimize the power dissipation in the event that pin LIN is short-circuited to ground. Only a weak pull-up between pins LIN and VBAT is present. Sleep mode can be activated independently from the actual level on pin LIN, pin TXD or pin WAKE_N. This guarantees that the lowest power consumption is achievable even in case of a continuous dominant level on pin LIN or a continuous LOW on pin WAKE_N. When VBAT drops below the power-on-reset threshold Vth(POR)L, the TJA1021 enters Sleep mode.
7.3 Standby mode
Standby mode is entered automatically whenever a local or remote wake-up occurs while the TJA1021 is in Sleep mode. These wake-up events activate pin INH and enable the slave termination resistor at the pin LIN. As a result of the HIGH condition on pin INH the voltage regulator and the microcontroller can be activated.
TJA1021
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Product data sheet
Rev. 6 -- 30 December 2010
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NXP Semiconductors
TJA1021
LIN 2.1/SAE J2602 transceiver
Standby mode is signalled by a LOW-level on pin RXD which can be used as an interrupt for the microcontroller. In Standby mode (pin SLP_N is still LOW), the condition of pin TXD (weak pull-down or strong pull-down) indicates the wake-up source: weak pull-down for a remote wake-up request and strong pull-down for a local wake-up request. Setting pin SLP_N HIGH during Standby mode results in the following events:
* An immediate reset of the wake-up source flag; thus releasing the possible strong
pull-down at pin TXD before the actual mode change (after tgotonorm) is performed
* A change into Normal mode if the HIGH level on pin SLP_N has been maintained for
a certain time period (tgotonorm)
* An immediate reset of the wake-up request signal on pin RXD 7.4 Normal mode
In Normal mode the TJA1021 is able to transmit and receive data via the LIN bus line. The receiver detects the data stream at the LIN bus input pin and transfers it via pin RXD to the microcontroller (see Figure 1): HIGH at a recessive level and LOW at a dominant level on the bus. The receiver has a supply-voltage related threshold with hysteresis and an integrated filter to suppress bus line noise. The transmit data stream of the protocol controller at the TXD input is converted by the transmitter into a bus signal with optimized slew rate and wave shaping to minimize EME. The LIN bus output pin is pulled HIGH via an internal slave termination resistor. For a master application an external resistor in series with a diode should be connected between pin INH or VBAT on one side and pin LIN on the other side (see Figure 7). When in Sleep, Standby or Power-up mode, the TJA1021 enters Normal mode whenever a HIGH level on pin SLP_N is maintained for a time of at least tgotonorm. The TJA1021 switches to Sleep mode in case of a LOW-level on pin SLP_N, maintained for a time of at least tgotosleep.
7.5 Wake-up
When VBAT exceeds the power-on-reset threshold voltage Vth(POR)H, the TJA1021 enters Power-on mode. Though the TJA1021 is powered-up and INH is HIGH, both the transmitter and receiver are still inactive. If SLP_N = 1 for t > tgotonorm, the TJA1021 enters Normal mode. There are three ways to wake-up a TJA1021 which is in Sleep mode: 1. Remote wake-up via a dominant bus state of at least twake(dom)LIN 2. Local wake-up via a negative edge at pin WAKE_N 3. Mode change (pin SLP_N is HIGH) from Sleep mode to Normal mode
7.6 Remote and local wake-up
A falling edge at pin LIN followed by a LOW level maintained for a certain time period (twake(dom)LIN) and a rising edge at pin LIN respectively (see Figure 4) results in a remote wake-up. It should be noted that the time period twake(dom)LIN is measured either in Normal mode while TXD is HIGH, or in Sleep mode irrespective of the status of pin TXD.
TJA1021 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 -- 30 December 2010
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NXP Semiconductors
TJA1021
LIN 2.1/SAE J2602 transceiver
A falling edge at pin WAKE_N followed by a LOW level maintained for a certain time period (twake(dom)WAKE_N) results in a local wake-up. The pin WAKE_N provides an internal pull-up towards pin VBAT. In order to prevent EMI issues, it is recommended to connect an unused pin WAKE_N to pin VBAT. After a local or remote wake-up, pin INH is activated (it goes HIGH) and the internal slave termination resistor is switched on. The wake-up request is indicated by a LOW active wake-up request signal on pin RXD to interrupt the microcontroller.
7.7 Wake-up via mode transition
It is also possible to set pin INH HIGH with a mode transition towards Normal mode via pin SLP_N. This is useful for applications with a continuously powered microcontroller.
7.8 Wake-up source recognition
The TJA1021 can distinguish between a local wake-up request on pin WAKE_N and a remote wake-up request via a dominant bus state. 'A local wake-up request sets the wake-up source flag. The wake-up source can be read on pin TXD in the Standby mode. If an external pull-up resistor on pin TXD to the power supply voltage of the microcontroller has been added, a HIGH level indicates a remote wake-up request (weak pull-down at pin TXD) and a LOW level indicates a local wake-up request (strong pull-down at pin TXD; much stronger than the external pull-up resistor). The wake-up request flag (signalled on pin RXD) as well as the wake-up source flag (signalled on pin TXD) are reset immediately after the microcontroller sets pin SLP_N HIGH.
7.9 TXD dominant time-out function
A TXD dominant time-out timer circuit prevents the bus line from being driven to a permanent dominant state (blocking all network communication) if pin TXD is forced permanently LOW by a hardware and/or software application failure. The timer is triggered by a negative edge on pin TXD. If the duration of the LOW-level on pin TXD exceeds the internal timer value (tto(dom)TXD), the transmitter is disabled, driving the bus line into a recessive state. The timer is reset by a positive edge on pin TXD.
7.10 Fail-safe features
Pin TXD provides a pull-down to GND in order to force a predefined level on input pin TXD in case the pin TXD is unsupplied. Pin SLP_N provides a pull-down to GND in order to force the transceiver into Sleep mode in case the pin SLP_N is unsupplied. Pin RXD is set floating in case of lost power supply on pin VBAT. The current of the transmitter output stage is limited in order to protect the transmitter against short circuit to pins VBAT or GND. A loss of power (pins VBAT and GND) has no impact on the bus line and the microcontroller. There are no reverse currents from the bus. The LIN transceiver can be disconnected from the power supply without influencing the LIN bus.
TJA1021
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Product data sheet
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TJA1021
LIN 2.1/SAE J2602 transceiver
The output driver at pin LIN is protected against overtemperature conditions. If the junction temperature exceeds the shutdown junction temperature Tj(sd), the thermal protection circuit disables the output driver. The driver is enabled again when the junction temperature has dropped below Tj(sd) and a recessive level is present at pin TXD. If VBAT drops below Vth(VBATL)L, a protection circuit disables the output driver. The driver is enabled again when VBAT > Vth(VBATL)H and a recessive level is present at pin TXD.
LIN recessive
VBAT
0.6VBAT VLIN 0.4VBAT LIN dominant ground sleep mode standby mode
001aae071
tdom(LIN)
Fig 4.
Remote wake-up behavior
TJA1021
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 -- 30 December 2010
9 of 25
NXP Semiconductors
TJA1021
LIN 2.1/SAE J2602 transceiver
8. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to pin GND; unless otherwise specified. Positive currents flow into the IC. Symbol VBAT VTXD VRXD VSLP_N VLIN VWAKE_N IWAKE_N VINH IO(INH) VESD Parameter battery supply voltage voltage on pin TXD voltage on pin RXD voltage on pin SLP_N voltage on pin LIN voltage on pin WAKE_N current on pin WAKE_N voltage on pin INH output current on pin INH electrostatic discharge voltage according to IEC 61000-4-2 human body model charge device model machine model Tvj Tstg Tamb
[1] [2] [3] [4]
[1]
Conditions with respect to GND ITXD no limitation ITXD < 500 A IRXD no limitation IRXD < 500 A ISLP_N no limitation ISLP_N < 500 A with respect to GND, VBAT and VWAKE_N only relevant if VWAKE_N < VGND 0.3 current will flow into pin GND
Min 0.3 0.3 0.3 0.3 0.3 0.3 0.3 40 0.3 15 0.3 50 8 2 750
[3] [4]
Max +40 +6 +7 +6 +7 +6 +7 +40 +40 VBAT +0.3 +15 +8 +2 +750 +200 +150 +150 +125
Unit V V V V V V V V V mA V mA kV kV kV V V C C C
on pins WAKE_N, LIN, VBAT and INH on pins RXD, SLP_N and TXD all pins all pins
[2] [2]
200 40 55 40
virtual junction temperature storage temperature ambient temperature
Equivalent to discharging a 150 pF capacitor through a 330 resistor. ESD performance of 6 kV for pins LIN, VBAT and WAKE_N is verified by an external test house. Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. Equivalent to discharging a 200 pF capacitor through a 10 resistor and a 0.75 H coil. Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tj = Tamb + P Rth(j-a), where Rth(j-a) is a fixed value. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
9. Thermal characteristics
Table 6. Thermal characteristics According to IEC 60747-1. Symbol Rth(j-a) Parameter thermal resistance from junction to ambient Conditions SO8 package; in free air HVSON8 package; in free air Typ 145 50 Unit K/W K/W
TJA1021
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Product data sheet
Rev. 6 -- 30 December 2010
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TJA1021
LIN 2.1/SAE J2602 transceiver
10. Static characteristics
Table 7. Static characteristics VBAT = 5.5 V to 27 V; Tvj = 40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1] Symbol Supply IBAT battery supply current Sleep mode VLIN = VBAT; VWAKE_N = VBAT VTXD = 0 V; VSLP_N = 0 V Standby mode; bus recessive VINH = VBAT; VLIN = VBAT VWAKE_N = VBAT; VTXD = 0 V VSLP_N = 0 V Standby mode; bus dominant VBAT = 12 V; VINH = 12 V VLIN = 0 V; VWAKE_N = 12 V VTXD = 0 V VSLP_N = 0 V Normal mode; bus recessive VINH = VBAT; VLIN = VBAT VWAKE_N = VBAT; VTXD = 5 V VSLP_N = 5 V Normal mode; bus dominant VBAT = 12 V; VINH = 12 V VWAKE_N = 12 V; VTXD = 0 V VSLP_N = 5 V Power-on reset Vth(POR)L Vth(POR)H Vhys(POR) Vth(VBATL)L Vth(VBATL)H Vhys(VBATL) Pin TXD VIH VIL Vhys RPD(TXD) IIL IOL HIGH-level input voltage LOW-level input voltage hysteresis voltage pull-down resistance on pin TXD LOW-level input current LOW-level output current VTXD = 5 V VTXD = 0 V local wake-up request Standby mode; VWAKE_N = 0 V VLIN = VBAT; VTXD = 0.4 V
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Parameter
Conditions
Min 2
Typ 7
Max 10
Unit A
150
450
1000
A
300
800
1200
A
300
800
1600
A
1
2
4
mA
LOW-level power-on reset threshold voltage HIGH-level power-on reset threshold voltage power-on reset hysteresis voltage LOW-level VBAT LOW threshold voltage HIGH-level VBAT LOW threshold voltage VBAT LOW hysteresis voltage
power-on reset
1.6 2.3 0.05 3.9 4.2 0.05
3.1 3.4 0.3 4.4 4.7 0.3
3.9 4.3 1 4.7 4.9 1
V V V V V V
2 0.3 50 140 5 1.5
200 500 -
7 +0.8 400 1200 +5 -
V V mV k A mA
TJA1021
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Product data sheet
Rev. 6 -- 30 December 2010
11 of 25
NXP Semiconductors
TJA1021
LIN 2.1/SAE J2602 transceiver
Table 7. Static characteristics ...continued VBAT = 5.5 V to 27 V; Tvj = 40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1] Symbol Pin SLP_N VIH VIL Vhys RPD(SLP_N) IIL IOL ILH Pin WAKE_N VIH VIL Ipu(L) ILH Pin INH Rsw(VBAT-INH) Standby; Normal and Power-on switch-on resistance between pins VBAT and INH modes; IINH = 15 mA VBAT = 12 V HIGH-level leakage current Sleep mode VINH = 27 V; VBAT = 27 V VBAT = 18 V; VLIN = 18 V VTXD = 0 V Sleep mode; VSLP_N = 0 V VLIN = 27 V; VBAT = 5.5 V VTXD = 5 V Normal mode; VTXD = 5 V VLIN = 0 V; VBAT = 12 V in pull-up path with Rslave ISerDiode = 10 A VBAT = 27 V; VLIN = 0 V VBAT = 0 V; VLIN = 27 V
[2]
Parameter HIGH-level input voltage LOW-level input voltage hysteresis voltage pull-down resistance on pin SLP_N LOW-level input current LOW-level output current HIGH-level leakage current
Conditions
Min 2 0.3 50
Typ 200 500 0 0
Max 7 +0.8 400 1200 +5 +5
Unit V V mV k A mA A
VSLP_N = 5 V VSLP_N = 0 V Normal mode VLIN = 0 V; VRXD = 0.4 V Normal mode VLIN = VBAT; VRXD = 5 V
140 5 1.5 5
Pin RXD (open-drain)
HIGH-level input voltage LOW-level input voltage LOW-level pull-up current HIGH-level leakage current VWAKE_N = 0 V VWAKE_N = 27 V; VBAT = 27 V
VBAT 1 0.3 30 5 -
12 0 20
VBAT + 0.3 V VBAT 3.3 V 1 +5 50 A A
ILH Pin LIN IBUS_LIM Rpu IBUS_PAS_rec IBUS_PAS_dom
5
0
+5
A
current limitation for driver dominant state pull-up resistance receiver recessive input leakage current receiver dominant input leakage current including pull-up resistor voltage drop at the serial diodes loss of ground leakage current loss of battery leakage current receiver dominant threshold voltage receiver recessive threshold voltage center receiver threshold voltage
40 50 600
160 -
100 250 1 -
mA k A A
VSerDiode IL(log) IL(lob) Vth(dom)RX Vth(rec)RX Vth(RX)cntr
TJA1021
0.4 750 0.6VBAT
-
1.0 +10 1 0.4VBAT -
V A A V V
Vth(RX)AV = (Vth(rec)RX + Vth(dom)RX) / 2
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0.475VBAT 0.5VBAT 0.525VBAT V
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 -- 30 December 2010
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NXP Semiconductors
TJA1021
LIN 2.1/SAE J2602 transceiver
Table 7. Static characteristics ...continued VBAT = 5.5 V to 27 V; Tvj = 40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1] Symbol Vth(hys)RX Rslave CLIN Vo(dom) Parameter receiver hysteresis threshold voltage slave resistance capacitance on pin LIN dominant output voltage Normal mode; VTXD = 0 V VBAT = 7.0 V Normal mode; VTXD = 0 V VBAT = 18 V Thermal shutdown Tj(sd) shutdown junction temperature
[2]
Conditions Vth(hys)RX = Vth(rec)RX Vth(dom)RX connected between pins LIN and VBAT; VLIN = 0 V; VBAT = 12 V
[2]
Min 20 -
Typ 30 -
Max
Unit
0.175VBAT V 47 30 1.4 2.0 k pF V V
150
175
200
C
[1] [2]
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. Not tested in production; guaranteed by design.
11. Dynamic characteristics
Table 8. Dynamic characteristics VBAT = 5.5 V to 18 V; Tvj = 40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; see Figure 6; unless otherwise specified.[1] Symbol Duty cycles 1 duty cycle 1 Vth(rec)(max) = 0.744 VBAT Vth(dom)(max) = 0.581 VBAT tbit = 50 s; VBAT = 7 V to 18 V Vth(rec)(max) = 0.76 VBAT Vth(dom)(max) = 0.593 VBAT tbit = 50 s; VBAT = 5.5 V to 7.0 V 2 duty cycle 2 Vth(rec)(min) = 0.422 VBAT Vth(dom)(min) = 0.284 VBAT tbit = 50 s; VBAT = 7.6 V to 18 V Vth(rec)(min) = 0.41 VBAT Vth(dom)(min) = 0.275 VBAT tbit = 50 s; VBAT = 6.1 V to 7.6 V 3 duty cycle 3 Vth(rec)(max) = 0.778 VBAT Vth(dom)(max) = 0.616 VBAT tbit = 96 s; VBAT = 7 V to 18 V Vth(rec)(max) = 0.797 VBAT Vth(dom)(max) = 0.630 VBAT tbit = 96 s; VBAT = 5.5 V to 7 V
[2][3][4][7]
Parameter
Conditions
Min
Typ
Max -
Unit
0.396 -
[2][3][4][7]
0.396 -
-
[2][4][5][7]
-
-
0.581
[2][4][5][7]
-
-
0.581
[3][4][7]
0.417 -
-
[3][4][7]
0.417 -
-
TJA1021
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Product data sheet
Rev. 6 -- 30 December 2010
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TJA1021
LIN 2.1/SAE J2602 transceiver
Table 8. Dynamic characteristics ...continued VBAT = 5.5 V to 18 V; Tvj = 40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 12 V; see Figure 6; unless otherwise specified.[1] Symbol 4 Parameter duty cycle 4 Conditions Vth(rec)(min) = 0.389 VBAT Vth(dom)(min) = 0.251 VBAT tbit = 96 s; VBAT = 7.6 V to 18 V Vth(rec)(min) = 0.378 VBAT Vth(dom)(min) = 0.242 VBAT tbit = 96 s; VBAT = 6.1 V to 7.6 V Timing characteristics tf tr t(r-f) tPD(TX) tPD(TX)sym tPD(RX) tPD(RX)sym twake(dom)LIN twake(dom)WAKE_N tgotonorm fall time rise time difference between rise and fall time transmitter propagation delay transmitter propagation delay symmetry receiver propagation delay receiver propagation delay symmetry LIN dominant wake-up time dominant wake-up time on pin WAKE_N go to normal time Sleep mode Sleep mode time period for mode change from Sleep, Power-on or Standby mode into Normal mode
[6] [2][4] [2][4] [4][5][7]
Min -
Typ -
Max 0.590
Unit
[4][5][7]
-
-
0.590
5 2.5 2 30 7 2
80 30 5
22.5 22.5 +5 6 +2.5 6 +2 150 50 10
s s s s s s s s s s
VBAT = 7.3 V
[2][4]
[2]
[6]
tinit(norm) tgotosleep tto(dom)TXD
normal mode initialization time go to sleep time TXD dominant time-out time time period for mode change from Normal slope mode into Sleep mode VTXD = 0 V
5 2 27
5 55
20 10 90
s s ms
[1] [2] [3] [4] [5] [6] [7]
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. Not applicable for the /10 versions of the TJA1021.
t bus rec min 1 3 = ------------------------------2 t bit
Bus load conditions are: CL = 1 nF and RL = 1 k; CL = 6.8 nF and RL = 660 ; CL = 10 nF and RL = 500 .
t bus rec max 2 4 = ------------------------------- 2 t bit
Load condition pin RXD: CRXD = 20 pF and RRXD = 2.4 k. For VBAT > 18 V the LIN transmitter might be suppressed. If TXD is HIGH then the LIN transmitter output is recessive.
TJA1021
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Product data sheet
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TJA1021
LIN 2.1/SAE J2602 transceiver
VBAT WAKE_N SLP_N TXD RXD
RRXD CRXD
INH
100 nF RL
TJA1021
LIN GND
CL
001aae069
Fig 5.
Timing test circuit for LIN transceiver
tbit VTXD
tbit
tbit
tbus(dom)(max) VBAT
tbus(rec)(min)
Vth(rec)(max) LIN BUS signal Vth(dom)(max) Vth(rec)(min) Vth(dom)(min)
thresholds of receiving node 1
thresholds of receiving node 2
tbus(dom)(min) receiving node 1 VRXD
tbus(rec)(max)
tp(rx1)f receiving node 2 VRXD
tp(rx1)r
tp(rx2)r
tp(rx2)f
001aae072
Fig 6.
Timing diagram LIN transceiver
TJA1021
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Product data sheet
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LIN 2.1/SAE J2602 transceiver
12. Application information
ECU BATTERY LIN BUS LINE
+5 V/ +3.3 V
only for master node
INH VDD RX0 RXD 1 8 7
VBAT 3 WAKE_N
1 k
MICROTX0 CONTROLLER GND Px.x
TXD
4
TJA1021
6 LIN
(1) 001aae070
SLP_N
2
5
(1) Master: C = 1 nF; slave: C = 220 pF.
Fig 7.
Typical application of the TJA1021
13. Test information
Immunity against automotive transients (malfunction and damage) in accordance with LIN EMC Test Specification / Version 1.0; August 1, 2004. The waveforms of the applied transients are according to ISO7637-2: Draft 2002-12, test pulses 1, 2a, 3a and 3b.
13.1 Quality information
This product has been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and is suitable for use in automotive applications.
TJA1021
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 -- 30 December 2010
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TJA1021
LIN 2.1/SAE J2602 transceiver
14. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c
y
HE
vMA
Z
8 5
Q A2 A1
pin 1 index
(A 3) Lp L
A
1
4
e
bp
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75
0.069
A1 0.25 0.10
A2 1.45 1.25
A3 0.25
0.01
bp 0.49 0.36
c 0.25 0.19
D (1) 5.0 4.8
0.20 0.19
E (2) 4.0 3.8
0.16 0.15
e 1.27
0.05
HE 6.2 5.8
L 1.05
Lp 1.0 0.4
Q 0.7 0.6
v 0.25
0.01
w 0.25
0.01
y 0.1
0.004
Z (1) 0.7 0.3
0.028 0.012
8o o 0
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC
076E03
JEDEC
MS-012
JEITA
EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-18
Fig 8.
TJA1021
Package outline SOT96-1 (SO8)
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Product data sheet
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TJA1021
LIN 2.1/SAE J2602 transceiver
HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm
SOT782-1
X
D
B
A
E
A
A1 c
detail X terminal 1 index area terminal 1 index area 1 L K e1 e b 4 v w CAB C y1 C C y
Eh
8 Dh
5
0 Dimensions Unit(1) mm A A1 b c 0.2 D Dh E Eh e
1 scale e1 K
2 mm
L
v 0.1
w
y
y1 0.1
max 1.00 0.05 0.35 nom 0.85 0.03 0.30 min 0.80 0.00 0.25
3.10 2.45 3.10 1.65 0.35 0.45 3.00 2.40 3.00 1.60 0.65 1.95 0.30 0.40 2.90 2.35 2.90 1.55 0.25 0.35
0.05 0.05
Note 1. Plastic or metal protrusions of 0.075 maximum per side are not included. Outline version SOT782-1 References IEC --JEDEC MO-229 JEITA --European projection
sot782-1_po
Issue date 09-08-25 09-08-28
Fig 9.
TJA1021
Package outline SOT782-1 (HVSON8)
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Product data sheet
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LIN 2.1/SAE J2602 transceiver
15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards.
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
TJA1021 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 -- 30 December 2010
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TJA1021
LIN 2.1/SAE J2602 transceiver
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 16.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 10) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9 and 10
Table 9. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 10. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 10.
TJA1021
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
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TJA1021
LIN 2.1/SAE J2602 transceiver
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 10. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
17. Soldering of HVSON packages
Section 16 contains a brief introduction to the techniques most commonly used to solder Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON leadless package ICs can found in the following application notes:
* AN10365 `Surface mount reflow soldering description" * AN10366 "HVQFN application information"
TJA1021
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(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 -- 30 December 2010
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TJA1021
LIN 2.1/SAE J2602 transceiver
18. Revision history
Table 11. Revision history Release date 20101230 Data sheet status Product data sheet Change notice Supersedes TJA1021 v.5 Document ID TJA1021 v.6 Modifications:
* * * *
TJA1021TK/10 and TJA1021TK/20 versions added Table 1, Table 5, Table 7, Table 8: parameter values/conditions/notes updated Section 17 "Soldering of HVSON packages": added Section 19 "Legal information": updated Product data sheet Product data sheet Product data sheet Preliminary data sheet Objective data sheet TJA1021 v.4 TJA1021 v.3 TJA1021 v.2 TJA1021 v.1 -
TJA1021 v.5 TJA1021 v.4 TJA1021 v.3 TJA1021 v.2 TJA1021 v.1
20091022 20090119 20071008 20070903 20061016
TJA1021
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 -- 30 December 2010
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TJA1021
LIN 2.1/SAE J2602 transceiver
19. Legal information
19.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
19.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be
TJA1021
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Product data sheet
Rev. 6 -- 30 December 2010
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TJA1021
LIN 2.1/SAE J2602 transceiver
Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TJA1021
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Product data sheet
Rev. 6 -- 30 December 2010
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LIN 2.1/SAE J2602 transceiver
21. Contents
1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 10 11 12 13 13.1 14 15 16 16.1 16.2 16.3 16.4 17 18 19 19.1 19.2 19.3 19.4 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Low power management . . . . . . . . . . . . . . . . . 1 Protection mechanisms . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Remote and local wake-up . . . . . . . . . . . . . . . . 7 Wake-up via mode transition . . . . . . . . . . . . . . 8 Wake-up source recognition . . . . . . . . . . . . . . . 8 TXD dominant time-out function . . . . . . . . . . . . 8 Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal characteristics . . . . . . . . . . . . . . . . . 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 16 Test information . . . . . . . . . . . . . . . . . . . . . . . . 16 Quality information . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Handling information. . . . . . . . . . . . . . . . . . . . 19 Soldering of SMD packages . . . . . . . . . . . . . . 19 Introduction to soldering . . . . . . . . . . . . . . . . . 19 Wave and reflow soldering . . . . . . . . . . . . . . . 19 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 20 Soldering of HVSON packages. . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact information. . . . . . . . . . . . . . . . . . . . . 24 21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 30 December 2010 Document identifier: TJA1021

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